Intel officially introduced its first Gemini Lake chips based on the new Goldmont Plus microarchitecture earlier this month. But apart from promising some improvements for wireless networks, battery life, and displays, the company didn’t tell us much about how the new chips are actually different from the Apollo Lake processors they’ll replace.
Now the company has released a document aimed at developers, with some of the information they’ll need to optimize software to run on the company’s latest chips… including upcoming processors based on the new Goldmont Plus architecture.
I’ll be honest. Some of this stuff is way over my head, so I’m just going to copy and paste the list of things Intel says it’s done to make Goldmont Plus better than the Goldmont architecture that powered Apollo Lake chips.
- Widen previous generation Atom processor back-end pipeline to 4-wide allocation to 4-wide retire, while maintaining 3-wide fetch and decode pipeline.
- Enhanced branch prediction unit.
- 64KB shared second level pre-decode cache (16KB in Goldmont microarchitecture).
- Larger reservation station and ROB entries to support large out-of-order window.
- Wider integer execution unit. New dedicated JEU port with support for faster branch redirection.
- Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides.
- Improved AES-NI instruction latency and throughput.
- Larger load and store buffers. Improved store-to-load forwarding latency store data from register.
- Shared instruction and data second level TLB. Paging Cache Enhancements (PxE/ePxE caches).
- Modular system design with four cores sharing up to 4MB L2 cache.
- Support for Read Processor ID (RDP) new instruction.
We also know there will be at least 6 new chips at launch, including 2 Celeron chips for mobile devices, 2 for desktops, and 2 Pentium Silver chips, one for mobile and one for desktop devices.
thanks anonymous tipster!