Intel officially introduced its first Gemini Lake chips based on the new Goldmont Plus microarchitecture earlier this month. But apart from promising some improvements for wireless networks, battery life, and displays, the company didn’t tell us much about how the new chips are actually different from the Apollo Lake processors they’ll replace.

Now the company has released a document aimed at developers, with some of the information they’ll need to optimize software to run on the company’s latest chips… including upcoming processors based on the new Goldmont Plus architecture.

I’ll be honest. Some of this stuff is way over my head, so I’m just going to copy and paste the list of things Intel says it’s done to make Goldmont Plus better than the Goldmont architecture that powered Apollo Lake chips.

  • Widen previous generation Atom processor back-end pipeline to 4-wide allocation to 4-wide retire, while maintaining 3-wide fetch and decode pipeline.
  • Enhanced branch prediction unit.
  • 64KB shared second level pre-decode cache (16KB in Goldmont microarchitecture).
  • Larger reservation station and ROB entries to support large out-of-order window.
  • Wider integer execution unit. New dedicated JEU port with support for faster branch redirection.
  • Radix-1024 floating point divider for fast scalar/packed single, double and extended precision floating point divides.
  • Improved AES-NI instruction latency and throughput.
  • Larger load and store buffers. Improved store-to-load forwarding latency store data from register.
  • Shared instruction and data second level TLB. Paging Cache Enhancements (PxE/ePxE caches).
  • Modular system design with four cores sharing up to 4MB L2 cache.
  • Support for Read Processor ID (RDP) new instruction.

We also know there will be at least 6 new chips at launch, including 2 Celeron chips for mobile devices, 2 for desktops, and 2 Pentium Silver chips, one for mobile and one for desktop devices.

thanks anonymous tipster!

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11 replies on “Intel outlines changes in the architecture for upcoming Gemini Lake chips”

  1. They basically claim that they’ve improved IPC (instruction per clock), and that these cpu have more space in their workbench (4x more in some aspects), the parameters that might interest developers the most are the ones with numbers describing them.

    1. Atom has come a long way. The latest Atom CPUs are now lower Watts but faster than my Ivy Lake i3 ULV CPU. Add in the Gemini Lake’s support for HEVC/VP9, 10bit video and HDMI 2.0…. These are really useful CPU for a lot of different use cases.

      1. Spot on…depending on the usage case and the price of the device, all the 4 cores Atoms since bay trail have provided basic utility in many super cheap devices with low energy usage. It will be interesting to see If ARM processors have any impact on that space…for Inhell it is about profit not performance, they would hâve to be sweeting a bit now!

  2. Are there any benchmarks that focus on Chromebook performance or NAS performance? Good benchmarks should be able to show the efficacy of the above new features. I care about system performance, not SOC performance.

      1. I got a speedometer score of 57 on my haswell 2955u chromebox running ubuntu and Chrome 63.
        n3350 (dual core apollo lake) got a score of 35.
        n3160 (quad core braswell) got a score of 28.
        Multiple cores do almost nothing in terms of javascript app performance.
        MediaTek MT8173C got a score of 40.
        RK3399 got a score of 32.

        My point is that if you want low power consumption, pick an ARM chromebook. If you want performance, pick a core celeron chromebook (or faster). For browser app performance (and general performance) 2 big cores are much better than 4 small ones.

  3. Its just architectural description. Intel has to show they are doing something, but the real test isn’t physical description, its how it really operates in different conditions in the real world. If you have a big pipe but the water doesn’t flow, doesn’t matter how big the pipe is does it?

    1. Chips are actual tangible physical objects and software people who live in math and abstraction have a hard time getting that through their head. Architecture is just a guidebook, a standard, a snapshot, nothing more. No two chips, even on the same production line and design, are identical anyway.

      1. So what’s your point?
        Seems like two otherwise useless comments.
        Is the J K shorthand for “joke”?

Comments are closed.