Samsung and Qualcomm may be some of the first chip makers to bring 10nm processors to market, but Intel wants you to know that not all chips built using a 10nm process are the same… and that its upcoming 10nm chips will be “a full generation ahead” of the competition.
Basically the idea is that a move to a new node should result in doubling the transistor density, improving performance and efficiency. Intel says it’s doing that with the move from 14nm chips to 10nm chips… but claims that competitors are not.
Overall, Intel says its upcoming 10nm chips will offer up to 25 percent better performance and use 45 percent less power than equivalent chips manufactured using 14nm technology… and that’s before you account for other features Intel is baking into its upcoming chips that should boost performance even more.
This doesn’t mean that the latest chips from Qualcomm or Samsung, or upcoming MediaTek processors won’t benefit from the transition to 10nm. But the gains might be more modest in some situations.
Of course, this is largely a discussion of transistor density. There are plenty of other differences between Intel’s upcoming 10nm chips for laptop, desktop, and server computers and the 10nm ARM-based chips for smartphones and other mobile devices that mean comparing an Intel Cannonlake processor and a Qualcomm Snapdragon 835 chip might be like comparing bananas and plantains (sure, there are similarities, but you generally eat them in very different ways).
Wow, you would think that GPU customers would be beating down Intel’s door to get access to that awesome process. Hasn’t happen before and I would not expect it in the future either. Nvidia and AMD are doing just fine performance wise not using an Intel process. I really couldn’t​ care less about what marketing says… performance speaks louder than words.
Great. Now all I need is to do is find a use for all those floating point adders and dozen mov instructions, vectorize and unroll all my loops with pure assembly and rewrite everything else in C++ since only templates has any hope at taking advantage of all those proprietary instructions.
RISC always had less logic transistors then CISC. That’s the whole point of using fewer and more generic instructions. To free up space for cache and allow flexible and generic programming and easier branch prediction. It’s literally the text-book answer…
Honestly, who comes up with this stuff?
Your compilers don’t unroll for you? Damn. I could use the extra floating point adders if you’re not using ’em.
There are other advantages to RISC and CISC on RISC. But since space is less of a limitation, maybe it’s time to start reexamining RISC.
Computer engineers come up with this stuff. Did you actually not know that? Do you think reduced power consumption is not worth it?
>Your compilers don’t unroll for you?…
If you think your compiler is properly unrolling your loops I suggest you crack open that dusty ol’ debugger and take a look at the assembly. Both GCC and VisualC++ fail to unroll most loops. If they could, we’d all be using EPICItaniums by now and your GPU would still be a VLIW instead of a RISC.
As for floating point adders, there’s plenty of studies doing statistical analysis on general purpose code showing those are under-used 80% of the time outside of server farms. It’s why you won’t find too many of those on mobile SoCs or even desktops to some extent.
>Do you think reduced power consumption is not worth it?
That’s 45% off Intel’s equivalent 14nm. Compared to their competition they’re still behind by a long stretch.
I did check GCC output meticulously when writing my data processing programs. It did unroll loops properly where I needed them.
Like I said, if you’re not doing float math, give the adders to me. I’ll make use of them.
So… because they’re behind the competition… progress isn’t worth it? Might as well give up and just throw all the other performance advantages in the bin? Ok.
I think you analogy would have been better if you had used (sour) grapes.