AMD is showing off technology that could dramatically increase the amount and speed of cache memory available for next-gen chips, with up to 192MB of L3 cache on upcoming AMD Ryzen desktop chips and support for bandwidth of over 2 terabytes per second.

In terms of real-world performance, AMD says that will bring the same kind of performance boost we’d normally expect from a move from one chip architecture to the next (from Zen 3 to Zen 4, for example).

In a demo during the company’s Computex 2021 keynote event, AMD showed two computers running the same video game. Both systems featured Ryzen 9 5900X 12-core processors running at 4 GHz and both were using the same graphics card.

But one card was a standard Ryzen 9 5900X with 64MB of L3 cache, while the other was a modified version with 192 MB of L3 cache. That model achieved frame rates that were 12-percent higher. And that’s on the low end of what AMD is promising – the company says across a range of games, it’s seeing an average 15-percent boost in frames per second.

AMD says the increase in memory capacity and speed comes from its 3D chiplet technology, developed with TSMC. It allows the memory to be stacked in a way that allows big increases in density and bandwidth. At 2TB/s, the L3 cache is actually faster than the L1 cache, although the latency is higher.

In a chip like the Ryzen 9 5900X with three CPU core clusters, the new 3D chiplet technology allows AMD to place a stack of 64MB of L3 cache on top of each core cluster for a total of 192MB.

AMD says it will begin production of its “highest end products with 3D chiplets” by the end of this year, suggesting we could see next-gen processors featuring the new technology in late 2021 or early 2022.

via AMD press release, AMD video, AnandTech, and Tom’s Hardware 

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    1. This is way better than on-package memory, such as Intel’s Crystal Well 128 MB eDRAM on some Core products. Since it is direct silicon to silicon stacking, you get orders of magnitude faster bandwidth and lower latency.

      1. I find it interesting that Apple M1 does not use chiplets for external cache, but instead uses the packaging for improved sdram performance. The lower sdram latency and higher throughput probably is beneficial all the time, where a large L3 might have diminishing returns.

  1. AMD is knocking the socks off Intel right now.
    AMD was my first build back in the 90’s, and AMD has always held a special place in my heart.
    It’s good to see the underdog winning for once.

    I just got a new ryzen system, and I’m really surprised by the performance improvement over my last system. I couldn’t be happier with it!

  2. I foresee a time when operating systems load into the L3 cache completely. You could easily stick an entire linux kernel in there with 192 MB, as L3 will seriously smoke out off-chip DRAM, yes even latest greatest DDR-5 or PCIE. Its a matter of distance. Vertical stacking throws the limits to the dogs and closes CPU gaps with FPGAs.

    1. Of course both memory and processor produce copious heat, so mitigation techniques are paramount when putting hot on hot.