Intel’s Atom line of low-power processors are getting a major update this year with the introduction of the company’s new Tremont architecture. Last year Intel provided some basic details about the upcoming processors, but now we have more information thanks to the chip maker’s latest x86/x64 Software Optimization Manual (PDF link).

In a nutshell, expect significant boosts in both performance and power management.

Keep in mind that Tremont chips still part of Intel’s Atom line, which means the emphasis is on low price and low power consumption, not necessarily bleeding edge performance. So don’t expect Celeron and Pentium processors with Tremont CPU cores to be competitive with Intel’s higher-performance Core processors or AMD’s latest Ryzen chips.

But the lines between Atom and Core may be blurring a bit — Intel’s Lakefield processor, for example is expected to power a handful of upcoming premium devices including the Microsoft Surface Neo and the Lenovo ThinkPad X1 Fold. The Lakefield chip will have a single Sunny Cove CPU core (the same architecture used in 10th-gen Intel Core “Ice Lake” processors), and four Tremont CPU cores.

In other words, Tremont might not just be designed for low-cost laptops, Chromebooks, and mini PCs anymore… although it’ll likely show up in some of those as well.

Intel has previously said we can expect Tremont to offer 30-percent boost in performance over its previous-gen Goldmont+ architecture (used in low-power chips first introduced in 2017). But here’s are some notes from the Software Optimization Model that explain how the new 10nm+ chip architecture will do that:

  • “Tremont microarchitecture supports many of the same features as those found on the Ice Lake Client microarchitecture.”
  • Tremont will be the first Intel Atom processors to support Intel Speed Shift technology.
  • Support for parallel out-of-order instruction decode
  • An increase in the size of reorder buffer, load buffer, store buffer, and reservation stations for deeper out-of-order execution and higher cache bandwidth
  • 33-percent increase in the size of L1 data cache (from 24KB to 32KB)
  • 100-percent increase in the load bandwidth and store bandwidth
  • L2 cache sizes ranging from 1MB to 4.5MB depending on the SoC design
  • Support for new instructions for encryption, power management, cache, and more

 

via @InstLatX64

 

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