The MediaTek Helio X20 is expected to be one of the first 10-core mobile processors when the chip launches later this year.
We first heard about the upcoming processor from Taiwanese chip maker MediaTek about a week ago. Now a few more details are emerging, giving us an idea of what to expect from the many-core chip.
According to slides shared at Chinese social networking site Weibo, the chip will feature:
- Two 2.5 GHz ARM Cortex-A72 CPU cores
- Four 2 GHz ARM Cortex-A53 CPU cores
- Four 1.4 GHz ARM Cortex-A53 CPU cores
All of those processor cores are based on ARMv8 64-bit architecture, but the fastest chips are based on ARM’s latest designs which are said to offer up to 3.5 times the performance of an ARM Cortex-A15 processor while using up to 75 percent less power.
The Cortex-A53 cores are still pretty speedy, but they offer less performance and consume less power. Like most ARM-based chips with four or more processors, the Helio X20 will use only as many cores as needed for a certain task. The lower-power cores can handle day-to-day tasks with the higher-performance components kicking into action only when they’re needed. This helps mobile devices balance battery life and performance.
ARM calls its version of this technology big.LITTLE, but MediaTek says it’s upcoming chip uses a tri-cluster arrangement which offers even greater power consumption savings.
We’ll have to wait until the MediaTek Helio X20 (also known as the MTK6797) chip is released in the second half of 2015 to know whether this is all just a marketing gimmick or if ten cores are really better than eight (or four, for that matter). But MediaTek claims the new chip will score over 70,000 in the AntTuTu benchmark, while the company’s Helio X10 chip cores closer to 50,000.
via GizmoChina
10 cores “seem” excessive but I’m no engineer.
I will leave judgement for real world performance/cost.
If devices which employ this architecture are cheaper or the same price and performance is similar or better than whatever’s on the market currently but also offer sufficiently extended run times then obviously this makes a ton of sense.
If not, then this to me would be chalked up to being gimmicky.
Logically speaking, I can see how 3 clusters may work out to be better performance-wise as long as the software is smart and quick enough at switching between everything. As it is right now though, the whole 2 cluster 4+4 scenario doesn’t seem to be any better than just using a quad core. If you look at benchmarks, they are both so similar that by the end of it, you’ll likely be using graphics performance or battery longevity as the qualifier of what you want to purchase. So a 10 core for me would have to really prove to me that it’s better on one of these fronts.
Nobody claims better perf with the 3 stages just better power consumption.
SD615 is like this except missing the big cores and (it appears) Qualcomm hasn’t done much to optimize the lower clocked cores for low power but a lot more could be done.
A quad cluster including cache on 20nm might be about 4.5mm2 die area so not a lot but hard to say if it’s worth it or not, that will depend on how much power they save and how much perf they lose will all the core switching.
A53 was aimed at about 1.2GHz and above that power consumption goes up fast. The A53s at 1.4GHz might be almost 3 times lower perf than the A72 at 2.5GHz and that would be a big perf gap.So a mid stage makes some sense for both power and perf.
They likely could have went 2+2+2 but then the cache for each cluster would have been rather small and adding more would result in very little die area saved vs 4+4+2 since getting rid of just 4 cores but keeping the cache should save less than 3mm2. With more cores it’s better on the marketing side and maybe in some rare cases for the users too.
In any case the cool part is the A72 perf not the number of cores.
Don’t focus on the number of cores, there are more interesting things than that here.
The latest Geekbench scores from the dual A72 tab SoC from Mediatek https://browser.primatelabs.com/geekbench3/compare/2378944?baseline=2375021
The MT8173 is supposed to max at 2.4GHz and almost 1700 in single core is very very nice from a midrange tab SoC. The Galaxy S6 single core perf is about 1500. SD801 some 1000 and A53 at 1.7GHz some 800+.
And that’s a dev board, final perf could be better.
The phone SoC , if real, has slightly higher clocks and would gain in perf further because of the wider (128 bit) memory bus.
And that’s the interesting part here, there is a huge gain in perf.
That’s pretty excessive..Why not just 2 A72’s at 2.5 and then something like 4 A53’s at 2 with some kind of dynamic clock speeds that scale the A53’s speed based on how light the demands are? Seems ridiculous to have 3 clusters on a single chip. Am I wrong on any of what I said being possible and more feasible? I’m all for squeezing as many cores as possible into a chip because if it were used in a PC or server system it could be very useful, but I think this is ridiculous given the market Mediatek usually sells to.
I agree. Three clusters is just unnecessary: When I’m using a phone or tablet, there’s only 2 use cases: 1) I need maximum performance (gaming) or 2) I need maximum battery life (everything else). I honestly don’t see the need for more granularity than that.
If it was up to me, I’d have 2 to 4 A72’s (each dynamically turned on or off depending on load), and 1 core of whatever is most energy efficient at 500mhz.
This is simply not true. Do you use web browser? Do you use navigation? Do you work with pohotos or movies? For all this you need good performance but not the highest possible all the time.
I don’t know how efficient this is. Of course the 10 cores are there also because of marketing. But wait for real world results before you judge so strictly.
not saying whether it’s a good idea or not to have 2 sets of A53’s at different max speeds, but one reason to do that is if you target different A53 max speeds, you can use different transistors in the design. An A53 that has a max speed of 2G might need for example a LVT (low VT) transistor in order to hit that speed, and even though the 2G can drop down to 1.4G, it still won’t be as efficient as using a HVT (high VT) transistor that originally targeted 1.4G in the design
personally I don’t think that’s an efficient use of die size, but I’m not paid big bucks to decide that.
i second that.
latest marketing gimmick from mediatek? we’ll see when it is released